The present invention relates to measuring jitter in digital data, and more particularly to jitter measurement using a mixed down topology.
As serial data stream rates become ever increasing in frequency, it is more difficult to measure the jitter at the serial data baud. Traditional jitter measurement systems first recover the clock from the serial data stream with a wide-band phase-locked-loop (PLL) clock recovery system that preserves the jitter to be measured. The recovered clock is then divided down to some sub-rate clock whose jitter is measured relative to some stable internal reference clock.
Two major drawbacks to this traditional jitter measurement system arise as the serial bauds become faster. First, the ability to recover the clock using a wide-band PLL or an injection-locked oscillator system becomes too costly and the components required to work at these higher clock rates are not readily available. Second, when the higher baud clock is recovered and then divided down, the amount of jitter to be measured in time is maintained. For example if a 10 giga-bits per second (Gb/s) serial data stream has 10 picoseconds (ps) of jitter, i.e., 0.1 UI (Unit Interval=one clock period), and then the recovered clock is divided down to 1 giga-Hertz (GHz), the divided down clock still maintains the 10 ps of jitter from the original 10 GHz recovered clock. The problem now is that the 10 ps relative to the lower speed 1 GHz clock is 0.01 UI. To measure this small amount of jitter requires a jitter measurement system with very low intrinsic jitter.
What is desired is a jitter measurement system that is relatively inexpensive while maintaining the relative jitter as a fraction of the UI during the process when the bauds of the serial data stream are high.